Metal oxide semiconductor field effect transistors (MOSFETs) that break conventional characteristics limitations are being developed using a superjunction structure. In fabricating (manufacturing) these superjunction MOSFETs (SJMOSFETs), epitaxial layers are separately grown on a semiconductor substrate multiple times, and at each growth session, alternating parallel p-type regions and n-type regions are repeatedly formed by patterning and ion implantation. At the time of the repeated epitaxial growth and the patterning and ion implantation, regions of the same type among the p-type regions and the n-type regions are connected in a thickness direction, forming a pn column structure extending in a direction orthogonal to a main surface of the substrate is a most characterizing aspect of a method of manufacturing a so-called superjunction semiconductor device. A method of manufacturing a superjunction MOSFET having a pn column structure formed by such a method is referred to as a multi epitaxial method. Nonetheless, this technique has issues in that processes are complex, manufacturing cost is high, and chip cost is high.
On the other hand, recently, a method of manufacturing a superjunction MOSFET by a technique that embeds an epitaxial layer in a trench and reduces manufacturing cost is being developed. FIG. 16 is a cross-sectional view of a structure of a conventional superjunction MOSFET. As depicted in FIG. 16, a superjunction MOSFET uses a wafer in which an n-type drift layer 102 is grown on an n++-type semiconductor substrate 101 of a high impurity concentration. A p-type pillar region 103 is provided from a surface of this wafer. The p-type pillar region 103 penetrates the n-type drift layer 102 and does not reach the n++-type semiconductor substrate 101. In FIG. 16, although the p-type pillar region 103 does not reach the n++-type semiconductor substrate 101, the p-type pillar region 103 may reach the n++-type semiconductor substrate 101.
According to one method, as a semiconductor material, a 4-layer periodic hexagonal silicon carbide (4H-SiC) is used and when the p-type pillar region 103 is formed, a trench is formed in the n-type drift layer 102 and a p-type impurity is re-embedded in the trench by epitaxial growth.
An n-type CS layer (carrier storage) 105 is provided on the n-type drift layer 102, and a p-type base layer 106 is provided at a surface of the n-type CS layer 105. A trench 1018 is provided at a front surface side of the p-type base layer 106. Along a side wall of the trench 1018, a gate insulating film 109 is provided, and a gate electrode 1010 is provided on the gate insulating film 109. A bottom of the trench 1018 is in contact with the p-type pillar region 103. Further, an n+-type source region 107 and a p+-type contact region 108 are provided in the p-type base layer 106. Further, a source electrode 1011 is provided on the n+-type source region 107 and the p+-type contact region 108, and a drain electrode 1012 is provided on a rear surface of the n++-type semiconductor substrate 101.
In FIG. 16, a SJ layer 1021 has in the n-type drift layer 102, a parallel structure (hereinafter, parallel pn layer) in which a p-type region (the p-type pillar region 103) extending in a direction orthogonal to a main surface of the substrate and having a narrow width in a direction parallel to the main surface of the substrate and an n-type region (a part of the n-type drift layer 102 between p-type pillar regions 103) are arranged repeatedly alternating in a direction parallel to the main surface of the substrate. Even when the p-type regions and the n-type regions constituting the parallel pn layer are each low resistance regions formed from a high impurity concentration, the p-type regions and the n-type regions are set at an interval that is narrow to an extent that with a low breakdown voltage in an OFF state, a depletion layer spreading from pn junctions of all of the p-type regions and the n-type regions in the parallel pn layer promptly depletes the entire parallel pn layer. For example, as a charge balance of the p-type regions and the n-type regions, an arithmetic product of the width of the p-type pillar region 103 and the impurity concentration of the p-type pillar region 103 is substantially equal to an arithmetic product of the width of the n-type region and the impurity concentration of the n-type region. Therefore, the SJ layer 1021 is known as a structure that concurrently obtains both characteristics of low ON resistance and high breakdown voltage characteristics.
For example, according to one technique, in a superjunction semiconductor device, an impurity concentration of a p-RESURF layer is set so that distribution (sloped profile) thereof decreases in a depth direction, whereby a breakdown voltage decrease with respect to an amount of unbalance between an impurity amount of the p-RESURF layer and an impurity amount of the n−-type drift layer is reduced as compared a conventional case (for example, refer to Patent Document 1).